Recent advances in semiconductor fabrication techniques have dramatically increased the density and speed of semiconductor devices, leading to a concomitant effort in the field of semiconductor packaging, where increased device density gives rise to many challenges related to electrical connectivity, heat-transfer, manufacturability, and the like. In this regard, a major trend in semiconductor packaging is toward low-profile, high-density device packages such as chip-scale and stacked-die packages.
A typical stacked-die package includes two or more semiconductor devices configured in a stack—one on top of the other—with bond wires leading from bond pads on the first device to bond pads on the second. The bottom-most die in the stack is bonded to a suitable substrate, for example, a ball grid array (BGA) or fine ball grid array (FBGA) substrate, and bond wires are provided between bond-pads on the package substrate to one or more of the die in the stack. The BGA includes an array of solder balls which provide electrical connectivity to external devices. In this way, a relatively dense, low-profile semiconductor package can be manufactured.
Currently known stacked-die packages are unsatisfactory in a number of respects. For example, it is often difficult to properly form the numerous bond wires required between the various semiconductor devices and the package substrate. The complicated topology of wiring between the die and package substrate often results in crossed wires (as seen from a plan view of the die), shallow wire angles (i.e., where the angle between the bond wire and the active-surface of the device is very small), and exceedingly tight bond-pitch.
More particularly, referring to FIG. 1, a typical prior art stacked-die arrangement includes (in part) a bottom semiconductor device 104 mounted on a package substrate 106, and a top semiconductor device 102 mounted on bottom semiconductor device 104. A number of bond pads (e.g., bond pads 108) are provided on top semiconductor device 102 as well as bottom semiconductor device 104 and package substrate 106 (e.g., bond pads 110 and 112 respectively). A plurality of bond wires are formed between semiconductor device 104, semiconductor device 102, and package substrate 106. Due to the number and relatively tight pitch of the bond pads, the placement of bond wires leads to a number of manufacturability problems. As depicted in this drawing, for example, wires leading from bond pads 130 and 132 cross at a point 131 above package substrate 106. Furthermore, wires leading from bond pads 120, 126, and 128 are “interlaced,” resulting in difficult bonding targets and leading to wires which are undesirably close together. In addition, as bond wires must be formed from the package substrate 106 to the top-most die on the stack (102), these wires (e.g., wires 136 and 138) are often undesirably long—extending 4.5 mm or more.
Furthermore, to accomodate the complex connectivity in a stacked die package, known methods typically use a package substrate that includes four layers or more, i.e., multiple layers of metal circuitry providing connectivity between bond pads on the package substrate. Such package substrates are costly and time-consuming to design and fabricate.
Other prior art methods which are similarly undesirable include the use of redistribution layers incorporated into on one or more of the semiconductor die themselves, and/or the use of organic package substrates on a leadframe to connect multiple chips lying in a single plane on that leadframe.
Methods are therefore needed in order to overcome these and other limitations of the prior art. Specifically, there is a need for an improved and highly manufacturable stacked-die package.